This short article provides a brief summary of the current status of high speed wireline links and its future trend. It also captures the motivating factors for recent changes and explains the fundamental reasons behind it. Lower SNR in multilevel modulation has motivated recent change in the link architecture developed in leading R & D groups and differentiating features. Lastly, it points out the challenges to motivate future research work in academia and industry.

Keywords: wireline, inter-symbol-interference, modulation

ISI, inter symbol interference; CTLE, continuous time linear equalization; DFE, decision feedback equalization; FFE, feed-forward equalization

We are at a historical cross road in technology roadmap where the numbers of objects connected through internet have vastly outnumbered the human network. This network of smart objects, also known as IoT, will shape our life in the next decade and beyond. By 2020, the number of smart objects is expected to reach 100 million sending massive information over internet. To accommodate such user demand, data centers are also evolving both electrical and optical links are adopting complex modulation schemes. Eventually the need for higher speed from the users, service provider and equipment manufacturer motivates the researchers to push the limit of semiconductor device physics and communication theory. Ultimately, the end product is a fully integrated monolithic solution capable of transmitting and receiving terabits of information. Few example of such market driven R & D development efforts are given in Figure 1. While the particular development trend in each company may vary based on their business strategy, one consistent trend is the rapid increase in data rate over time. Figure also includes example work from these efforts and that also capture underline motivating factors:

1. All of them are designed for massive parallel interface, with clear indication that we need to achieve higher individual link speed as well as high density to aggregate higher information exchange rate.
2. Beyond 40 Gb/s almost everyone is converging to higher order (PAM-4) modulation.
3. All these transceivers are built in leading nodes in CMOS technology as continuation of Moore’s law.

Figure 1 Trend in High speed Link development in leading research and development groups in the world. Below is the example demonstration developed hardware solution with performance summary.

Over last two decades wire-line channels have evolved drastically to overcome high frequency losses. High frequency loss causes the transmitted symbols to disperse which results in inter-symbol-interference (ISI). The techniques to reduce these ISI components are known as equalization. The recent advances in interconnect technology and development of low loss dielectric such as Megatron have significantly extended their reach. This improvement in channel along with advances in equalization techniques have enables 100 Gb/s Ethernet. Improving the loss characteristics of channel increases system cost as shown in Figure 2. However, industry is facing an inevitable challenge despite using expensive lowest loss material and high quality connectors, only few 10s of cm channels suffering 45 dBs of loss @ 25 GHz. Such channel loss causes significant inter symbol interference (ISI), and existing equalization techniques are proving to be insufficient to compensate that. Unfortunately, this also aligns with the end of Moore’s law; therefore, we can no longer rely on higher performance devices to overcome the challenges. This creates an opportunity for disruptive technology and architecture.

In high-speed wireline transceivers, the frequency dependent channel loss is the main source of inter-symbol interference (ISI). In simple word, ISI is the residue of the current symbol that affects the following symbols (pre-cursor) as well as the previous symbols (post-cursor). For high loss channel, conventional receiver designs usually feature analog linear equalization techniques such as continuous time linear equalization (CTLE) and passive equalization at the front end as shown in Figure 3. In addition, decision feedback equalization (DFE) and feed-forward equalization (FFE) techniques are used for further ISI cancellation and bit detection. Fundamentally, this limitation is coming from degradation of low signal-to-noise and signal-to-crosstalk ratio that is unavoidable in existing equalization techniques. Analog mixed-signal solution in general can equalize with excellent energy efficiency (around ~3pJ/bit).³ But these solutions have their limitations: first, SNR degradation CTLE that generally inverts the channel also amplifies noise, including crosstalk noise and degrades SNR. Second, the linearity requirement scaled supply reduces maximum achievable linear swing. Third, process variation makes it very difficult to achieve reliable control over zero and pole frequencies to achieve the desirable frequency response. All these factors limit the performance of existing equalization techniques and ultimately our demonstrated capability of equalization is limited to 40 dB (Figure 4).

Figure 3 Conventional Analog mixed signal links and ADC based links.

Figure 4 Trend in Equalization techniques at different data rates and channel loss.

The equalization becomes more complicated when we move to higher order modulation as PAM-4 for several reasons

1. Compared to binary/PAM-2 signaling, the eye height reduces by 3x for the same transmit power - this translates to 9 dB SNR penalty and corresponding BER degradation.
2. Linearity requirement for PAM-4 signaling is much more stringent, that makes analog processing much more challenging compared to NRZ signaling although the supply is scaling with technology.
3. Residue ISI has much bigger impact in PAM-4 compared to NRZ. This is because residue of the largest transition impacts the smallest bit both as ISI and crosstalk that is 3x larger compared to NRZ.^2-5

All these challenges motivate us to rethink the equalization strategy as well as receiver architecture. Recently ADC based architectures are gathering interest to enhance performance through digital processing. Therefore, in ADC based receivers where equalization is done digitally, can take advantage of the technology scaling, enables advanced equalization that can compensate higher loss compared to traditional mixed signal equalization. However, the challenge in this architecture is the front-end ADC that consumes significant power to provide the required resolution. When compared to traditional mixed signal receiver, ADC based solutions’ power consumption is 2x higher.^6-13 Fortunately, recent trend is to improve their energy efficiency significantly, most of those are enabled through academic research and development that allows flexibility for disruptive approaches (Figure 5). Given the strict energy efficiency target, application of ADC based links depends on successful adoption of these techniques.

Figure 5 Energy efficiency trend in ADC based links for wireline communication.

None.

The author declares no conflict of interest.

1. Toifl T, Menolfi C, Ruegg M, et al. A 2.6 mW/Gbps 12.5 Gbps RX with 8–Tap Switched–Capacitor DFE in 32 nm CMOS. IEEE J Solid–State Circuits. 2012;47(4):897–910.
2. Cui D, Zhang H, Huang N, et al. 3.2 A 320mW 32Gb/s 8b ADC–based PAM–4 analog front–end with programmable gain control and analog peaking in 28nm CMOS. 2016 IEEE International Solid–State Circuits Conference (ISSCC), San Francisco, USA; 2006. p. 58–59.
3. ToiflC T, Menolfi C, Ruegg M, et al. A 22–gb/s PAM–4 receiver in 90–nm CMOS SOI technology. IEEE Journal of Solid–State Circuits. 2006;41(4):954–965.
4.  Frans Y, Elzeftawi M, Hedayati H, et al. A 56Gb/s PAM4 wireline transceiver using a 32–way time–interleaved SAR ADC in 16nm FinFET. VLSI Circuits, Honolulu, USA; 2016. p. 1–2.
5. Taft RC, Tursi MR. A 100–MS/s 8–b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V. IEEE Journal of Solid–State Circuits. 2001;36(3):331–338.
6. Abiri B, Sheikholeslami A, Tamura H, et al. A 5Gb/s adaptive DFE for 2x blind ADC–based CDR in 65nm CMOS. Solid–State Circuits Conference, San Francisco, USA; 2011. p. 436–438.
7. Chen EH, Yousry R, Yang CKK. Power Optimized ADC–Based Serial Link Receiver. IEEE J Solid–State Circuits. 2012;47(4):938–951.
8. Ting C, Liang J, Sheikholeslami A, et al. A blind baud–rate ADC–based CDR. IEEE Journal of Solid–State Circuits. 2013;48(12):122–123.
9.  Varzaghani A, Kasapi A, Loizos DN, et al. A 10.3–GS/s, 6–Bit Flash ADC for 10G Ethernet Applications. IEEE Journal of Solid–State Circuits. 2013;48(12):3038–3048.
10. Tabasy EZ, Shafik A, Lee K, et al. A 6 bit 10 GS/s TI–SAR ADC With Low–Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications. IEEE Journal of Solid–State Circuits. 2014;49(11):2560–2574.
11. Zhang B, Khanoyan K, Hatamkhani H, et al. 3.1 A 28Gb/s multi–standard serial–link transceiver for backplane applications in 28nm CMOS, Solid– State Circuits Conference – (ISSCC), 2015 IEEE International. San Francisco, USA; 2015. p. 1–3.
12.  Rylov S, Beukema T, Deniz ZT, et al. 3.1 A 25Gb/s ADC–based serial line receiver in 32nm CMOS SOI. Solid–State Circuits Conference (ISSCC), 2016 IEEE International. San Francisco, USA; 2016. p. 56–57.
13. Shafik A, Tabasy EZ, Cai S, et al. 3.6 A 10Gb/s hybrid ADC–based receiver with embedded 3–tap analog FFE and dynamically–enabled digital equalization in 65nm CMOS. Solid–State Circuits Conference–(ISSCC), 2015 IEEE International. San Francisco, USA; 2015. p. 1–3.