Review Article

Volume 2 Issue 4

Nano complementary metal oxide semi-conductor (CMOS) using carbon nanotube

Manu Mitra

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Electrical Engineering Department, Alumnus of University of Bridgeport, USA

**Received:** July 18, 2018 | **Published: ** November 27, 2018

**Correspondence: **
Manu Mitra, Electrical Engineering Department, Alumnus of University of Bridgeport, CT – 06604, USA

**Citation: **
Mitra M. Nano complementary metal oxide semi-conductor (CMOS) using carbon nanotube.

* Electric Electron Tech Open Acc J*. 2018;2(4):302‒308.
DOI:

10.15406/eetoaj.2018.02.00032
# Abstract

Complementary Metal Oxide Semiconductor (CMOS) is normally used to describe small measure of memory on a Computer motherboard that stores the Basic Input and Output Settings (BIOS) settings. Some of these BIOS settings include the system time and date and in hardware settings. CMOS is also used for constructing integrated circuits. It is normally used for microprocessors, micro controller and other digital circuits. In this review paper of Nano CMOS, its VI characteristics, data analysis and performances are discussed and graphs are depicted.

**Keywords:** nano, nanotechnology, nano CMOS

# Introduction

Complementary Metal Oxide Semiconductor (or simply called as CMOS) is used to design various logic circuits such as switches, inverter, transmission, NAND, NOR, XOR gates including compound logic, Static Random Access Memory (SRAM) Cells, registers etc. There are N-type and P-type transistors. P-type uses electrons and N-type uses holes. The gate of CMOS is made of aluminum alternatively, polysilicon can be used. Silicon dioxide is the substantial between gate and channel. Semiconductor material is mostly silicon alternatively, GaAs can also be used based on the applications and design.^{1}

Unlike any other BIPOLAR circuits, a Complementary MOS circuit has almost no static power scattering. Power is just dissipated if circuit switches "ON" or "OFF". This allows integrating more CMOS logic gates on an IC than bipolar technologies, resulting better performance. Complementary Metal Oxide Semiconductor transistor comprises of P-channel MOS (PMOS) and N-channel MOS (NMOS) (Figure 1).^{2}

**Figure 1 **Depicts traditional CMOS transistor.

**Nano complementary metal oxide semiconductor **

Carbon nanotubes can be metallic or semiconductor based on their chirality (Figure 2–4).

**Figure 2 **Depicts carbon nanotube.

**Figure 3 **Depicts Chirality of Carbon nanotube.

**Figure 4 **Depicts construction of complementary metal oxide semiconductor using carbon nanotubes.

**Characteristics of nano complementary metal oxide semiconductor**^{3,4 }(Figure 5–12).

**Figure 5 **Depicts the graph of N type for 32nm size (I_{ds} vs V_{ds}).

**Figure 6 **Depicts the graph of N type for 32nm (I_{ds} vs V_{gs}).

**Figure 7 **Depicts the graph of P type for 32nm (I_{ds} vs V_{ds}).

**Figure 8 **Depicts the graph of P type for 32nm (I_{ds} vs V_{gs}).

**Figure 9 **Depicts the graph of N type for 45nm (I_{ds} vs V_{ds}).

**Figure 10 **Depicts the graph of N type for 45nm (I_{ds} vs V_{gs}).

**Figure 11 **Depicts the graph of P type for 45nm (I_{ds} vs V_{ds}).

**Figure 12 **Depicts the graph of P type for 45nm(I_{ds} vs V_{gs}).

**Data analysis**

Data Analysis was performed for N-Type and P-Type for various voltages (0.01v, 25v, 50v) and performances for (I_{D} vs V_{DS}) and (I_{D} vs V_{GS}) are plotted (Figure 13–24).

**Figure 13 **Depicts the graph of N type (I_{D} vs V_{DS}) at 0.01 V.

**Figure 14 **Depicts the graph of N type (I_{D} vs V_{GS}) at 0.01 V.

**Figure 15 **Depicts the graph of P type (I_{D} vs V_{DS}) at 0.01 V.

**Figure 16 **Depicts the graph of P type (I_{D} vs V_{GS}) at 0.01 V.

**Figure 17 **Depicts the graph of N type (I_{D} vs V_{DS}) at 25 V.

**Figure 18 **Depicts the graph of N type (I_{D} vs V_{GS}) at 25 V.

**Figure 19 **Depicts the graph of P type (I_{D} vs V_{DS}) at 25 V.

**Figure 20 **Depicts the graph of P type (I_{D} vs V_{GS}) at 25 V.

**Figure 21 **Depicts the graph of N type (I_{D} vs V_{DS}) at 50 V.

**Figure 22 **Depicts the graph of N type (I_{D} vs V_{GS}) at 50 V.

**Figure 23 **Depicts the graph of P type (I_{D} vs V_{DS}) at 50 V.

**Figure 24 **Depicts the graph of P type (I_{D} vs V_{GS}) at 50 V.

# Results

A. Interpretation of Graphs

In Figure 14 (I_{D} vs V_{GS}) the purple color graph, current (I_{D}) has a sudden increase in spike and has steep fall and maintains constant at 1400 (approx.) because of very low voltage (0.01V).

In Figure 15 (I_{D} vs V_{GS}) the blue color graph, current (I_{D}) has a sudden slope and raises it and maintains constant at 1500 (approx.) because of very low voltage (0.01V).

# Conclusion

In this review paper what is claimed are:

VI Characteristics of nano complementary metal oxide semi-conductor for an N Type and P Type (32nm) (I_{ds} vs V_{ds}) are plotted.

VI Characteristics of nano complementary metal oxide semi-conductor for an N Type and P Type (32nm) (I_{ds} vs V_{gs}) are plotted.

VI Characteristics of nano complementary metal oxide semi-conductor for an N Type and P Type (45nm) (I_{ds} vs V_{ds}) are plotted.

VI Characteristics of nano complementary metal oxide semi-conductor for an N Type and P Type (45nm) (I_{ds} vs V_{gs}) are plotted.

Data Analysis of nano complementary metal oxide semi-conductor for an N Type and P Type (I_{D} vs V_{DS}) at 0.01V.

Data Analysis of nano complementary metal oxide semi-conductor for an N Type and P Type (I_{D} vs V_{GS}) at 0.01V.

Data Analysis of nano complementary metal oxide semi-conductor for an N Type and P Type (I_{D} vs V_{DS}) at 25V.

Data Analysis of nano complementary metal oxide semi-conductor for an N Type and P Type (I_{D} vs V_{GS}) at 25V.

Data Analysis of nano complementary metal oxide semi-conductor for an N Type and P Type (I_{D} vs V_{DS}) at 50V.

Data Analysis of nano complementary metal oxide semi-conductor for an N Type and P Type (I_{D} vs V_{GS}) at 50V.

# Acknowledgements

Author would like to thank Prof. Navarun Gupta, Prof. Hassan Bajwa, Prof. Linfeng Zhang and Prof. Hmurcik for their academic support. Author also thanks anonymous reviewers for their comments.

# Conflict of interest

The author declares there is no conflicts of interest.

# References

© 2018 Mitra. This is an open access article distributed under the terms of the

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