A new structure for comparator-based switched-capacitor integrator (CBSCI) is presented. This structure increases the clock frequency considerably by using a non-linear current source. The proposed integrator involves replacing the two linear current sources in conventional CBSCI with just one non-linear current source. Also new logic part is presented which reduces the circuit size and power dissipation consequently. According to proposed structure, a first order CBSCI is designed in 0.18µm CMOS technology with a 100MHz clock frequency.

Keywords: comparator-based switched-capacitor, integrator, non-linear current source

Most of switched-capacitor based circuits use operational amplifiers (OPAMP) for utilization and OPAMP gain is the most important criterion for the accuracy of these kinds of circuits.¹ While the scaling down of supply voltage and channel length of CMOS technology limit the design procedure. Gain and voltage swing are the main problems which both have been reduced. So finding an alternative for OPAMPs is a possible strategy to avoid imposed restrictions by advancement of CMOS technology. Comparator-Based Switched-Capacitor circuits are kinds of circuits which have removed OPAMP and instead of it use a comparator and current sources. These circuits have shown higher power efficiency and are unconditionally stable due to removed feedback. The most valuable feature of an OPAMP is the virtual ground effect that should be simulated in CBSCC to perform proper operations. In fact virtual ground detection for inputs of comparator is the major concentration in these circuits. This can be realized by extra circuit which includes current sources and logic control part. Some techniques have introduced to reduce the CBSCC delay issue. Lower common mode voltage for comparator inputs, using two comparators, common mode feedback, common mode feed forward, using an extra clock and overshoot correction circuit are presented in.^1,3–14 All the above techniques have failed to reduce delay time considerably or have designed in complicated extra circuitry. In this paper we have proposed a new technique to faster detection of virtual ground effect. New schemes for current sources and logic control part are explained and we have used this technique to design a CBSCI. This integrator can use to form a Sigma-Delta Modulator (SDM) which is the most important part of a Sigma-Delta analog to digital convertor.

Conventional CBSCI

The conventional CBSCI has shown in (Figure 1) consists of a comparator followed by a logic unit which generates control signals as E1 (coarse charge transfer), E2 (fine charge transfer), S (output switch), and P (preset switch).¹⁵ E1 and E2 are applied to two linear current sources, I1 and I2 which charge and discharge the load capacitor as coarse and fine charge transfer. The timeline of this integrator has shown in (Figure 2). According to (Figure 2) during the sampling phase the input signal has sampled in Cs and charge transfer phase begin with rising Ф2. In the beginning of this phase a preset pulse is applied to the output, connecting it to the lowest voltage in the circuit. Then a coarse charge transfer phase E1 and a fine charge transfer phase E2 charge and discharge the load capacitor respectively in order to creation of virtual ground effect. During the preset phase, the virtual ground node (the comparator positive input), Vx, drop below the common-mode voltage, Vcm, and resetting the comparator. The logic control part raises E1, and I1 charges the load capacitor (output node) up to the virtual ground node equals the common-mode voltage (coarse charge transfer). At this time, the comparator set, however the load capacitor has charged up higher than proper value due to the comparator delay time. So an overshoot error has produced which shown in (Figure 2). In order to correction extra charges the logic control part pull down the E1 and raises the E2 which cause to discharges the output node by I2 (fine charge transfer) which has slower rate compared with I1, until the virtual ground node voltage becomes lower than Vx, at this time the output of comparator resets again and both of E1 and E2 are came down. Here, switch S opens by logic control part and the correct value is sampled on the load capacitor (which is the sampling capacitor of the next stage).¹⁶ The output is slightly lower than the ideal value because of the comparator delay time. This delay time produces a constant signal-independent undershoot each cycle which shown in (Figure 2). In fact we need to reach the correct output value only at the sampling instant and it doesn’t matter how it reaches there. By this procedure we are able to detect the virtual ground effect in order to removing the OPAMPs.¹⁷ This strategy helps us to abandon issues of speed, gain, and stability. Replacing the OPAMP with comparator also has significant effect to power consumption issues due to lower power dissipation of comparators in comparison to OPAMPs.¹⁸

Figure 1 Schematic of Conventional CBSCI.

Figure 2 Time line of Conventional CBSCI.

Proposed CBSCI

The proposed CBSCI has shown in (Figure 3) which consists of sampling circuit, a comparator, a simple logic control part and a non-linear current source. The sampling circuit operates exactly like opamp-based switch capacitor circuit which sample the input signal and hold it for charge transfer phase, also logic control part include just three simple logic gates as three inputs and two inputs ANDs and an inverter. This logic control part is specified by red rectangular in (Figure 3). Also the main important part of this circuit is non-linear current source. This current source specified by green rectangular in (Figure 3), uses the M1 and M2 as switch and a PMOS transistor to drive large current as M5. Time line of this integrator has shown in (Figure 4) which shows logic signals and non-linear charging for virtual ground creation. According to (Figure 4) this circuit works in two main phases, the sampling phase and the charge transfer phase. In addition the charge transfer phase consists of two sub phases, the preset phase and the charge phase. During Ф1, the input signal is sampled and Ф2 begin with preset phase like conventional circuit and following the unique charge phase begins, which at the end of this sub phase S switch opens so the integration is performed. This integrator can operate with higher clock frequency due to unique charge phase.¹⁹ Also the logic part is miniaturized in compare with conventional circuit which reduces the circuit size and power consumption consequently. After sampling phase and in the beginning of Ф2, the P switch closes and output node connects to ground (the minimum voltage in the circuit). This cause the Vx becomes lower than Vcm so the comparator output set to high (inputs of comparator in proposed circuit are vice versa in comparison to conventional CBSCI). At this time outputs of ANDs, S and E are high and low respectively so the S switch is close and the gates of M1 and M2 are in low voltage which makes M1 off and M2 on considering that M1 is a NMOS and M2 is a PMOS transistor. So the gate of M4 as a PMOS type connects to supply voltage which makes it off and as a result the current mirror is off. In this condition M5 don’t charge the output node. Time of preset phase depends on capacitors connected to output node. In fact the preset phase is the appropriate time to discharge output node in order to reduce the Vx to lower voltage value than Vcm. This causes the value of Vx to go below the Vcm and consequently the output of the comparator is set to high. The next step is charge phase which has the most difference in this work in compare to other works. In this phase E and S is high so S switch is close and non-linear current source is working. The gates of M1 and M2 have high voltage so M1 is on and M2 is off. The gate of M4 connected to Vx which has lower value than Vcm at the beginning. So M4 is in triode region and has a current like (1).

$\left|I_{{}_{d4}}\right|={\mu }_{{}_p}{C}_{ox}{\left(\frac{W}{L}\right)}_{{}_4}\left(V_{{}_{GS}}-V_{thp}\right)V_{{}_{ds}}-\frac{1}{2}{V}_{{}_{ds}}^{{}^2}$(1)

Figure 3 Schematic of Proposed CBSCI with non-linear current source.

Figure 4 Time line of Proposed Integrator.

This current passes through M3 and copies to M5 and even can be amplify with current mirror gain. Finally the M5 charge output node by current which is proportional to Vx. This procedure charges the output node and Vx node consequently by through Cf. As the voltage of Vx is raising the source-gate voltage of M4 is falling so the current of M4 and M5 decrease respectively this can be cause changing in operation for M4 from triode to saturation and current can expresses by (2).

$\left|I_{{}_{d4}}\right|=\frac{1}{2}{\mu }_{{}_p}{C}_{ox}{\left(\frac{W}{L}\right)}_{{}_4}{\left(V_{{}_{GS}}-V_{thp}\right)}^{{}^2}\left(1+\lambda V_{{}_{ds}}\right)$(2)

Again by charging, the Vx increases and the current of M5 decreases, so a non-linear charging system creates. This non-linear charging continues the raising Vx voltage to the point that Vx reaches above than Vcm which changes the comparator output state. At this time the comparator output sets to low and current source is off and the S switch is open. So the charge transfer phase is completed. The comparator used in this circuit plays an important role to logic part stimulation. This comparator must have high speed and high resolution in order to be efficiently applicable in the proposed CBSCI at high clock frequency. The selected comparator in the proposed circuit shown in (Figure 5) includes three major part: source-coupled differential pair with positive feedback specified by red rectangular, differential to single-ended converter specified by green rectangular and output buffer specified by blue rectangular. The first part provides high resolution due to positive feedback. Also the differential to single-ended improves the gain of first part and finally the output buffer complete output node voltage swing.

Figure 5 Schematic of utilized comparator.

We designed proposed CBSC integrator in standard 0.18µm CMOS (Table 1) process and biased it with a 1.8V power supply voltage.²⁰ Non-overlapped clock frequencies, i.e. Ф1 and Ф2, choose 100MHz. Also input signal is a sinusoidal wave, has 1MHz frequency and 50mV amplitude. The sampling, feedback and load capacitor are 1pF, 4pF and 2pF respectively. (Figure 6) shows the input and output signals of proposed CBSC integrator with 100MHz clock frequency.²¹ In addition (Table 2) is presented to show the output phase in different sampling and input frequencies. To insure the accuracy of the proposed integrator we should check the Vx voltage and control signals which have been shown in (Figure 7). In this integrator comparator output trigger the non-linear current source and logic control part. Also the output of comparator depends on Vx as shown in (Figure 7). So in charge transfer phase when Vx is lower than common mode voltage (in this circuit selected equal to 0.65V) the comparator output is high and non-linear current source is working in order to charging output node and raising Vx respectively.²² when the Vx voltage be greater than common mode voltage, the comparator output set to low, non-linear current source is off and S switch opens as shown in (Figure 7).

Finally, (Table 3) shows the clock frequency and overshoots cancellation technique comparison between this work and previous works presented in literature. According to (Table 2) proposed integrator has higher clock frequency by using non-linear current source and simple logic part. In addition (Figure 8) shows the frequency spectral of output signal.²³

Figure 6 Input and output signals of proposed CBSC integrator in 100MHz clock frequency.

Figure 7 Vx and Control signals.

Figure 8 Frequency spectral of output signal.

A new structure for CBSC integrator has presented in this paper. Increasing the clock frequency was the major achievement, obtained by using a non-linear current source. Also a new logic part has introduced which is less complex in compare to previous works. The proposed integrator simulated in standard 0.18µm CMOS process and biased with a 1.8V power supply voltage with 100MHz clock frequency.^24,25

None.

The author declares no conflict of interest.

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